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2Gb: x16, x32 Mobile LPDDR2 SDRAM S4
Burst WRITE Command
Figure 41: Burst WRITE Followed by Burst READ – RL = 3, WL = 1, BL = 4
T0
T1
T2
T3
T4
T5
T6
T7
T8
CK#
CK
WL = 1
RL = 3
CA[9:0]
Bank m
col addr a
Col addr a
Bank n
col addr b
Col addr b
t WTR
CMD
WRITE
NOP
NOP
NOP
NOP
NOP
READ
NOP
NOP
DQS#
DQS
DQ
D IN A0
D IN A1
D IN A2
D IN A3
Transitioning data
Notes:
1. The minimum number of clock cycles from the burst WRITE command to the burst READ
command for any bank is [WL + 1 + BL/2 + RU( t WTR/ t CK)].
2. t WTR starts at the rising edge of the clock after the last valid input data.
3. If a WRITE burst is truncated with a BST command, the effective burst length of the
truncated WRITE burst should be used as BL to calculate the minimum WRITE-to-READ
delay.
Figure 42: Seamless Burst WRITE – WL = 1, BL = 4, t CCD = 2
T0
T1
T2
T3
T4
T5
T6
T7
T8
CK#
CK
WL = 1
CA[9:0]
Bank m
col addr a
Col addr a
Bank n
col addr b
Col addr b
t CCD
=2
CMD
WRITE
NOP
WRITE
NOP
NOP
NOP
NOP
NOP
NOP
DQS#
DQS
DQ
D IN A0
D IN A1
D IN A2
D IN A3
D IN B0
D IN B1
D IN B2
D IN B3
Transitioning data
Note:
1. The seamless burst WRITE operation is supported by enabling a WRITE command every
other clock for BL = 4 operation, every four clocks for BL = 8 operation, or every eight
clocks for BL = 16 operation. This operation is supported for any activated bank.
PDF: 09005aef83f3f2eb
2gb_mobile_lpddr2_s4_g69a.pdf – Rev. N 3/12 EN
64
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2010 Micron Technology, Inc. All rights reserved.
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制造商:Micron Technology Inc 功能描述:256MX32 LPDDR2 PLASTIC IND TEMP GREEN WFBGA 1.2V - Bulk